1. Field of the Invention
The present invention relates to a semiconductor device having electrode regions of high concentration and a method of manufacturing the same.
2. Description of the Background Art
FIG. 1 is a sectional view showing a conventional semiconductor device of isolated type composite element structure. As shown in FIG. 1, an insulated gate field-effect transistor 10A and a junction bipolar transistor 10B are formed in an upper layer part of an n.sup.- -type polysilicon substrate 1 to be insulated/isolated by insulating films 2. N.sup.+ -type layers 3 of prescribed thickness are formed on the insulating films 2, and n.sup.- -type layers 4 are formed on the n.sup.+ -type layers 3.
In an element forming region (hereinafter referred to as "island") provided with the field-effect transistor 10A, a p-type well region 5 is formed in an upper layer part of the n.sup.- -type layer 4, while n.sup.+ -type source regions 6 are selectively formed on the surface part of the p-type well region 5.
Polysilicon gates 8 are formed on surface parts of the p-type well region 5 held between the surfaces of the n.sup.- -type layer 4 and the source regions 6 through a gate oxide film 7. Drain electrodes 9 are formed on the surface of the n.sup.+ -type layer 3, and a source electrode 11 is formed over a part of the surface of the n.sup.+ -type source regions 6 and a part of the surface of the p-type well region 5 held between the n.sup.+ -type source regions 6, while gate electrodes 12 are formed on the polysilicon gates 8. The electrodes 9, 11 and 12 are insulated from each other by passivation films 18.
In another island provided with the bipolar transistor 10B on the other hand, a p-type base region 13 is formed in an upper layer part of the n.sup.- -type layer 4. An n.sup.+ -type emitter region 14 is formed in a part of the surface of the p-type base region 13. An emitter electrode 15 is formed on the n.sup.+ -type emitter region 14 and a base electrode 16 is formed on the p-type base region 13, while a collector electrode 17 is formed on the n.sup.+ -type layer 3. The electrodes 15 to 17 are insulated from each other by passivation films 18.
FIGS. 2A to 2G are sectional views showing a method of forming the islands in the semiconductor device shown in FIG. 1. This method will now be described with reference to these figures.
A resist film 22 is formed on the surface of a monocrystal n.sup.- -type substrate 21 as shown in FIG. 2A, and patterned as shown in FIG. 2B. The patterned resist film 22 serves as a mask to etch the n.sup.- -type substrate 21, thereby to define V-shaped cavities 23 as shown in FIG. 2C. An interval l between each pair of adjacent cavities 23 defines the width of each island.
Then, an n-type impurity such as phosphorus is diffused on the surface of the n.sup.- -type substrate 2 including the cavities 23, to form an n.sup.+ -type layer 3. Pretreatment (removal of a phosphorus glass layer etc. formed on the n.sup.+ -type layer 3) is performed through hydrofluoric acid system chemicals, and thereafter an insulating film 2 such as a thermal oxidation film is formed on the n.sup.+ -type layer 3, as shown in FIG. 2D.
An n.sup.- -type polysilicon layer 24 is formed on the insulating film 3 through epitaxial growth technique, as shown in FIG. 2E. Then, the rear surface of the n.sup.- -type substrate 21 is polished, to expose the insulating film 2 and the n.sup.+ -type layer 3 on the rear surface of the n.sup.- -type substrate 21, as shown in FIG. 2F.
Then, the n.sup.- -type substrate 21 is so turned over as to complete a plurality of islands 25, in which the n.sup.- -type polysilicon layer 24 corresponds to the n.sup.- -type polysilicon substrate shown in FIG. 1 and the remaining n.sup.- -type substrate 21 corresponds to the n.sup.- -type layers 4 shown in FIG. 1 while the respective islands 25 are insulated by the insulating films 2, as shown in FIG. 2G. The field-effect transistor 10A and the bipolar transistor 10B are manufactured in the respective islands 25 thus obtained.
The n.sup.+ -type layers 3, which are brought into ohmic contact with the drain electrodes 9 and the collector electrode 17, respectively, must be increased in thickness as well as in concentration in order to minimize ON resistance and drain-to-source forward voltage in the field-effect transistor 10A and to minimize collector-to-emitter saturation voltage in the bipolar transistor 10B.
However, it is extremely difficult to form thick n.sup.+ -type layers 3 of high concentration by an impurity diffusion method, since the processing takes too much time to degrade workability and since the value of concentration which can be realized through diffusion is limited to about 10.sup.18 to 10.sup.19 cm.sup.-3.